Ethernet switch Driver

The Ethernet switch is either a built in switch, or an external switch hardware
which ties to the processor. It allows for configuration of multiple ethernet
ports and configurations and setup of Switch related processes (such are VLANS,
ARL lookup, counter support).

Required properties:

- compatible:
    Must be "brcm,ethsw"

- reg: (for internal Ethernet switchs)
    entry    description
    1        Defines the base and size of the I/O address space of Switch
             registers
    2        Defines the base and size of the I/O address space of the LED
             control registers that work with the ports on the switch

- interrupts: (for internal Ethernet switchs)
    The interrupts of the ethernet switch hardware block.

- dev-name:
    Default name assigned as "ethsw".

- imp-port
    Defines which ports from the switch are connected to the processor.
    In some designs it is multiple ports, in others just one
    Integer value for port and speed
    port, speed
    port = port number of imp port being configured
	  speed = Speed of port connection. In most designes it is 2000 (2 gig)

- mii-port (design optional)
   Defines which port is the MII port on the switch as an INTEGER. Must
   correspond to the actual switch hardware as to which one is the mii port.
   port, ext, speed are the 3 settings all INTEGER
   port = port of the switch which is MII
   ext = specifies external phy
   speed = Speed at which port is to be configured too. Depends on switch
      hardware and design. In most cases it is fixed at 1000 (1 gig)

- eee-support
    Used to condigure EEE support in the switch chip or not

- high-speed-imp (design optional)
    Used to tell driver that the IMP port supports 2.5g speeds,
    internal switch design only

- phy-handles
    A phandle with phy handle reference corresponding to each
    name in the phy list.  This allows individual ports of the
    switch to be tied to a specific phy.
    References to all possible phy's on the
    switch chips supported. However, since the
    chips may or may not have the associated port & phy
    bonded out of the chip (i.e. the 53124 does not have
    port 0 bonded out) then they might not all be used
    53124 used sw_p1_phy..sw_p4_phy while 53134 uses
    sw_phy0_phy..sw_p3_phy.
    See documentation phy-bindings.txt

- subid-port-offset
    Sets the base port offset for this switch since there could be
    multiple ethsw in a design. If multiple Ethernet switches are defined
    then this offset needs to be set to show what the port offset would be,
    ie, if the first switch had already defined 4 ports, then the subid-port-offset
    for any new switch defined must start be 4

- spi-max-frequency (design optional)
    Defines maximum SPI frequency that the switch device can handle in Hz,
    only needs to be defined to switchs that are connected to SPI

- reg
    Defines which SPI address is tied too on the SPI bus for the switch

- size-cells
    See document booting-without-of.txt

- address-cells
    See document booting-without-of.txt

- default-vlan-mode (optional)
    This is an INTEGER value and can either be 0 or 1. If this is not included with
    the node, it will get defaulted to 1 (which is enabling vlans)

- rgmii-mode (design optional)
   INTEGER mode telling hardware if the rgmii is on or off. If this is not defined in
   node then it will be default the rgmii mode to off.

- phy-port-mask
   INTEGER value which contains a mask of which ports one the switch will actually be
   configured and used since not all ports have be used on a swith.  The phy port mask
   has the least significant bit representing the lowest port, and then progressing
   to the second bit being the second port etc etc. In this manner, the system can
   handle designs were ports are skipped (or not used)

Internal switch example:

	ethsw: ethsw@d4e00000 {
		compatible = "brcm,ethsw";
		reg = <0x0 0xd4e00000 0x0 0x42000>,
		      <0x0 0xd3c009c0 0x0 0x2c>;
		interrupts = <0 113 0>,
				<0 114 0>;
		dev-name = "ethsw";
		imp-port = <5 2000>,
			   <7 2000>,
			   <8 2000>;
		eee-support = <1>;
		high-speed-imp = <1>;
		phy-handles = <&sw_p0_phy>,
			      <&sw_p1_phy>,
			      <&sw_p2_phy>,
			      <&sw_p3_phy>;
		subid-port-offset = <0>;
		#size-cells = <1>;
		#address-cells = <0>;
		phy-port-mask = <0x5>;
	};

External switch example with parent being a SPI device

	ethsw@2 {
		reg = <2>;
		compatible = "brcm,ethsw";
		spi-max-frequency = <1563000>;
		dev-name   = "ethsw";
		mii-port   = <7 0 1000>;
		imp-port   = <8 1000>;
		eee-support = <1>;
		phy-handles = <&sw_p0_phy>,
			<&sw_p1_phy>,
			<&sw_p2_phy>,
			<&sw_p3_phy>,
			<&sw_p4_phy>;
		phy-port-mask = <0x5>;
		subid-port-offset = <0>;
	};
